As the development of the semiconductor fabrication technology tends to downsize the node, the layout pattern of the shallow ion implanting layer becomes smaller and smaller in size, and the pattern boundary becomes closer to the device in distance. However, it is easily to occur distortion for the pattern size due to the influence of the reflected light from the different material and morphology in a front layer of the bottom portion, which causes the reduction of the photoresist size, error implantation of ion into a device of photoresist covering region, or directly results in the stripping of the photoresist, to cause the failure of the ion implantation and become the yield killer. In particular, when an interval between patterns is smaller than 1.5˜3 times of the minimum size, there is a high possibility of forming hot spot, and it is easy to cause adverse effects such as photoresist collapse or inverse glue since the photoresist becomes narrow due to shrinkage after the subsequent exposure.
To solve the above problems, it is common action in the prior art to perform an Optical Proximity Correction (OPC) routine on the lithograph pattern according to wafer data, but there are defects in three aspects for the conventional Optical Proximity Correction:
(1) since the layout pattern is complicated and the influence of the reflect from the front layer is changeable, the amount of the collected wafer data is huge, which results in that it is very difficult to use the method of the Optical Proximity Correction to compensate and as a result, and there are still some potential problems to be leaved.
(2) Since the layout pattern of the shallow ion implanting layer are mostly generated by the logical operation, there are many useless pattern structures fallen on STI, and these pattern structures will not only increase the difficulty of the OPC routine and the operation amount, but also is the source which brings the process problems.
(3) Although these patterns fallen outside the shallow ion implanting region of a device are invalid, other special processing is not made on these patterns when layout design or logical operation is performed, only if they are in conformity with the design rules and requirement of the ion implantation of the device. That is, there are many invalid pattern structures to be remained. However, the correction on these invalid pattern structures will cause the waste of calculation resource of OPC, prolong the whole correction procedure, and thus affect the periods of the semiconductor process development.